The present invention relates to a time slot interchanger in a telephone system operating in time frames each consisting of a plurality of time slots.
Pulse code modulated (PCM) digital signals in a telephone system enable a multiplicity of conversations to be transferred over a two wire digitally multiplexed line commonly known as a T1 trunk line. The quantized PCM data representative of a sample of a particular portion of a conversation to be sent over a telephone trunk line between a calling and called party is serially interleaved or multiplexed with a number of other conversations into channels within a discrete time period. If 8 binary bits were to represent each quantized value, then up to 256 (2.sup.8) discrete values could represent the particular sample. The T1 trunk line comprises 24 multiplexed channels serially presented to a telephone switching system, with each conversation sampled at a frequency of 8 KHz (a period of 125 us). Each channel on the T1 line therefore is allocated a time slot of approximately 5.2 us. Serial T1 lines grounded together are further multiplexed into which is known as a line group. A line group will convert the serial PCM data to a parallel format. It is possible to switch a conversation on one channel or time slot of one line group to another channel or time slot of the same or other line group through a digital switch.
In prior art systems for PCM digital switching, multiplexed PCM data from a plurality of line groups is sent to a time slot interchanger.
Prior art time slot interchangers include first and second access lines with each access line connected to a number of PCM data buses via cross point switches. In addition, the prior art interchanger includes two data transfer memories associated with the access lines. The data transfer memories are alternately connected to the access lines through gating circuitry between successive time frames. Additional control memories are provided wherein two memories control cross point switch activation between the access lines and the data buses, and another memory controls the addressing of the data transfer memories.
The number of control memories, gating circuitry, and cross point switches required for prior art time slot interchangers necessarily affects the cost of the interchanger.
In accordance with the above background, it is desirable to have an improved and less expensive time slot interchanger capable of switching PCM data from one time slot to another time slot with less hardware than in the prior art.